Enum NnilInstruction 

pub enum NnilInstruction {
    Add {
        lhs: Insn,
        rhs: Insn,
    },
    Sub {
        lhs: Insn,
        rhs: Insn,
    },
    Mul {
        lhs: Insn,
        rhs: Insn,
    },
    Mulh {
        lhs: Insn,
        rhs: Insn,
    },
    Div {
        lhs: Insn,
        rhs: Insn,
    },
    Mod {
        lhs: Insn,
        rhs: Insn,
    },
    Fdiv {
        lhs: Insn,
        rhs: Insn,
        size: usize,
    },
    And {
        lhs: Insn,
        rhs: Insn,
    },
    Or {
        lhs: Insn,
        rhs: Insn,
    },
    Xor {
        lhs: Insn,
        rhs: Insn,
    },
    Sll {
        lhs: Insn,
        rhs: Insn,
    },
    Srl {
        lhs: Insn,
        rhs: Insn,
    },
    Sra {
        lhs: Insn,
        rhs: Insn,
    },
    Slt {
        lhs: Insn,
        rhs: Insn,
    },
    Mov {
        dst: Insn,
        src: Insn,
    },
    Set {
        dst: Insn,
        src: Insn,
    },
    Jr {
        dst: Insn,
    },
    Jmp {
        dst: Insn,
    },
    Beq {
        lhs: Insn,
        rhs: Insn,
        ttgt: Label,
        ftgt: Label,
    },
    Bne {
        lhs: Insn,
        rhs: Insn,
        ttgt: Label,
        ftgt: Label,
    },
    Blt {
        lhs: Insn,
        rhs: Insn,
        ttgt: Label,
        ftgt: Label,
    },
    Bgt {
        lhs: Insn,
        rhs: Insn,
        ttgt: Label,
        ftgt: Label,
    },
    Load {
        dst: Insn,
        src: Insn,
        size: u64,
    },
    Store {
        dst: Insn,
        src: Insn,
        size: u64,
    },
    Sext {
        size: usize,
        dst: Insn,
    },
    Zext {
        size: usize,
        dst: Insn,
    },
    Signed {
        dst: Insn,
    },
    Unsigned {
        dst: Insn,
    },
    IntToFloat {
        src: Insn,
        src_size: usize,
        signed: bool,
        dst_size: usize,
    },
    Imm {
        imm: i64,
    },
    Reg {
        reg: u64,
    },
    TmpReg {
        reg: u64,
    },
    Syscall {},
    Sysbreak {},
    Lr {
        dst: Insn,
        src: Insn,
        size: u64,
    },
    Sc {
        dst: Insn,
        src: Insn,
        addr: Insn,
        size: u64,
    },
    Amo {
        op: AmoOp,
        dst: Insn,
        src: Insn,
        addr: Insn,
        size: u64,
    },
    Fence {
        mode: u8,
        pred: u8,
        succ: u8,
    },
}

Represents guest semantics in a form that the JIT can emit directly.

Most operands are Insn handles. lhs and rhs are value inputs. A dst can be a value input or a write target, depending on the operation. Load, Mov, Set, LR, SC, and AMO use a register-like dst as a write target. The operation index is also its result handle.

Variants

Add

Adds two bit patterns with wrapping semantics because guest overflow does not panic.

Fields

lhs: Insn

Supplies the left input value.

rhs: Insn

Supplies the right input value.

Sub

Subtracts with wrapping semantics for the same guest-overflow rule.

Fields

lhs: Insn

Supplies the value to subtract from.

rhs: Insn

Supplies the value to subtract.

Mul

Produces the low backend-width part of an integer product.

Fields

lhs: Insn

Supplies the left factor.

rhs: Insn

Supplies the right factor.

Mulh

Produces the high backend-width part of a double-width product. Signedness markers on the operands select MULH, MULHSU, or MULHU behavior.

Fields

lhs: Insn

Supplies the left factor and its signedness marker.

rhs: Insn

Supplies the right factor and its signedness marker.

Div

Divides integer values. Operand markers select signed or unsigned behavior.

Fields

lhs: Insn

Supplies the dividend and its signedness marker.

rhs: Insn

Supplies the divisor and its signedness marker.

Mod

Produces an integer remainder. Operand markers select signed or unsigned behavior.

Fields

lhs: Insn

Supplies the dividend and its signedness marker.

rhs: Insn

Supplies the divisor and its signedness marker.

Fdiv

Divides IEEE floating-point bit patterns at the selected byte width.

Fields

lhs: Insn

Supplies the floating-point dividend bits.

rhs: Insn

Supplies the floating-point divisor bits.

size: usize

Selects the floating-point width as a byte count.

And

Performs bitwise AND without a signedness distinction.

Fields

lhs: Insn

Supplies the left input bits.

rhs: Insn

Supplies the right input bits.

Or

Performs bitwise OR without a signedness distinction.

Fields

lhs: Insn

Supplies the left input bits.

rhs: Insn

Supplies the right input bits.

Xor

Performs bitwise exclusive OR without a signedness distinction.

Fields

lhs: Insn

Supplies the left input bits.

rhs: Insn

Supplies the right input bits.

Sll

Shifts left and fills low bits with zero.

Fields

lhs: Insn

Supplies the value to shift.

rhs: Insn

Supplies the shift count.

Srl

Shifts right and fills high bits with zero.

Fields

lhs: Insn

Supplies the value to shift.

rhs: Insn

Supplies the shift count.

Sra

Shifts right and copies the sign bit into high bits.

Fields

lhs: Insn

Supplies the signed value to shift.

rhs: Insn

Supplies the shift count.

Slt

Returns one or zero for a less-than comparison. Operand markers tell the backend whether it must compare signed or unsigned values.

Fields

lhs: Insn

Supplies the left comparison value.

rhs: Insn

Supplies the right comparison value.

Mov

Copies a value to a write target.

Fields

dst: Insn

Selects the register-like write target.

src: Insn

Supplies the value to copy.

Set

Writes a computed value to a guest register or temporary target.

Fields

dst: Insn

Selects the guest register or temporary write target.

src: Insn

Supplies the value to write.

Jr

Transfers control to a computed address value and ends the current basic block.

Fields

dst: Insn

Supplies the computed guest target address.

Jmp

Transfers control to a direct or computed value and ends the current basic block.

Fields

dst: Insn

Supplies the direct or computed guest target address.

Beq

Branches to ttgt when two values are equal. Otherwise it branches to ftgt.

Fields

lhs: Insn

Supplies the left comparison value.

rhs: Insn

Supplies the right comparison value.

ttgt: Label

Selects the target when the values are equal.

ftgt: Label

Selects the target when the values differ.

Bne

Branches to ttgt when two values differ. Otherwise it branches to ftgt.

Fields

lhs: Insn

Supplies the left comparison value.

rhs: Insn

Supplies the right comparison value.

ttgt: Label

Selects the target when the values differ.

ftgt: Label

Selects the target when the values are equal.

Blt

Branches on less-than. Operand markers select signed or unsigned comparison.

Fields

lhs: Insn

Supplies the left comparison value.

rhs: Insn

Supplies the right comparison value.

ttgt: Label

Selects the target when lhs is less than rhs.

ftgt: Label

Selects the other target.

Bgt

Branches on greater-than. Operand markers select signed or unsigned comparison.

Fields

lhs: Insn

Supplies the left comparison value.

rhs: Insn

Supplies the right comparison value.

ttgt: Label

Selects the target when lhs is greater than rhs.

ftgt: Label

Selects the other target.

Load

Reads size bytes at address src and writes the result through dst. A later Unsigned marker requests zero extension. Integer loads otherwise sign-extend.

Fields

dst: Insn

Selects the register-like target for the loaded value.

src: Insn

Supplies the guest source address.

size: u64

Selects the memory width as a byte count.

Store

Writes the low size bytes of src to address dst.

Fields

dst: Insn

Supplies the guest destination address.

src: Insn

Supplies the value whose low bytes are stored.

size: u64

Selects the memory width as a byte count.

Sext

Sign-extends the low size bytes to the backend value width.

Fields

size: usize

Selects the input width as a byte count.

dst: Insn

Supplies the value to extend.

Zext

Zero-extends the low size bytes to the backend value width.

Fields

size: usize

Selects the input width as a byte count.

dst: Insn

Supplies the value to extend.

Signed

Marks a value for signed arithmetic without changing its bits.

Fields

dst: Insn

Supplies the value that later arithmetic must interpret as signed.

Unsigned

Marks a value for unsigned arithmetic without changing its bits.

Fields

dst: Insn

Supplies the value that later arithmetic must interpret as unsigned.

IntToFloat

Converts an integer value to an IEEE floating-point bit pattern.

Fields

src: Insn

Supplies the integer bits to convert.

src_size: usize

Selects the integer source width as a byte count.

signed: bool

Selects signed or unsigned integer interpretation.

dst_size: usize

Selects the floating-point result width as a byte count.

Imm

Creates a constant. Signed storage keeps negative RISC-V immediates direct.

Fields

imm: i64

Stores the signed constant directly.

Reg

Reads one architectural register. The backend enforces special rules such as x0.

Fields

reg: u64

Selects a register in the combined integer and floating-point namespace.

TmpReg

Reads one translator-private temporary register without using a guest register number.

Fields

reg: u64

Selects a translator-private temporary index.

Syscall

Returns control to the runtime for an execution-environment call.

Sysbreak

Returns control to the runtime for a guest breakpoint.

Lr

Loads a value and starts an atomic reservation for the addressed memory. The current Rust backend does not keep reservation state, which is an implementation limit.

Fields

dst: Insn

Selects the register-like target for the loaded value.

src: Insn

Supplies the guest source address.

size: u64

Selects the access width as a byte count.

Sc

Stores through a reservation and writes the success code through dst. The current Rust backend always reports success because it does not model reservations.

Fields

dst: Insn

Selects the target for the architectural success code.

src: Insn

Supplies the value to store.

addr: Insn

Supplies the reserved guest address.

size: u64

Selects the access width as a byte count.

Amo

Performs one atomic read-modify-write operation and returns the old memory value.

Fields

op: AmoOp

Selects how the loaded and source values form the stored value.

dst: Insn

Selects the target for the old memory value.

src: Insn

Supplies the value combined with memory.

addr: Insn

Supplies the guest memory address.

size: u64

Selects the access width as a byte count.

Fence

Carries guest memory-order information even when a single-threaded backend needs no code.

Fields

mode: u8

Keeps extension-specific fence mode bits.

pred: u8

Selects predecessor access classes that must complete first.

succ: u8

Selects successor access classes that must start later.

Trait Implementations

impl Clone for NnilInstruction

fn clone(&self) -> NnilInstruction

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for NnilInstruction

impl Debug for NnilInstruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for NnilInstruction

impl PartialEq for NnilInstruction

fn eq(&self, other: &NnilInstruction) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for NnilInstruction