Enum RiscVArch 

pub enum RiscVArch {
    Rv32,
    Rv64,
    Rv128,
}

Selects the register width because decoding and word-result rules depend on XLEN.

XLEN is the width of an integer register and a guest address calculation. RV32 uses 32 bits. RV64 uses 64 bits, and RV128 uses 128 bits. Some instruction encodings have a different meaning at different XLEN values, especially compressed and *W instructions. The runtime currently requests RV64 only. RV32 and the draft RV128 path expose incomplete decoder work, and NNIL values and addresses remain u64.

Variants

Rv32

Uses 32-bit integer registers and address calculations.

Rv64

Uses 64-bit integer registers and address calculations.

Rv128

Selects the draft 128-bit decode rules, which the current NNIL cannot represent fully.

Trait Implementations

impl Clone for RiscVArch

fn clone(&self) -> RiscVArch

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RiscVArch

impl Debug for RiscVArch

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for RiscVArch

impl PartialEq for RiscVArch

fn eq(&self, other: &RiscVArch) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for RiscVArch